Power comsumption when Vdd on GPIO when imp is off


I’d like to know if I could have a power consumption on the pad, if while the imp is off there is still a signal (Vdd, clock…) on a GPIO pin.

I gess it is a kind of backup mode, while the core supply of the chip is off.
In that case, is there some supply on the pads or not? Except the interrupt pin of course.


The imp has fail-safe IO. There is minimal leakage (no back-powering) if when the imp is unpowered the gpio PIN is still driven externally.

Hi Hugo,

Thank you for your answer. That’s perfect.