Current IMP sleeping while pins are floating

Is it true that, while IMP sleeps, the quiescent current increases when the I/O pins are floating?

When any CMOS chip is powered and pins float, the quiescent current can increase. This is due to the pad drivers getting in partially enabled states or oscillating.

The ST datasheet does not make it clear whether the IO ring power is gated when the chip is in standby mode; if it is gated, then these wouldn’t be necessary from a power consumption point of view when sleeping, unless you have IO attached that expects certain pin states.

As usually you do have IO attached to the imp, It’s good practice to have weak pullups/downs where necessary on designs; if nothing else, this ensures consistent behaviour during power up, impOS upgrade, etc.

The reason I asked was because I have a BLE113 breakout board that drawed 20uA. When I applied a pull up on uart rx the current reduced to 0.2uA as expected. 100k should not harm the communication at all. Thanks Hugo.

Yep, that sounds like a pin leakage amount of current. Also, the pull-up (which will only have current flowing through during serial transmission, as serial idles high) will prevent the device seeing spurious break signals when the imp is asleep.

I think that Impee-BLE112 also need some pullups-downs in case IMP is sleeping.

Ow but that doesn´t matter because Impee-BLE112 is not battery powered

Yeah, the imp doesn’t sleep in those cases (though good point, if we do a battery powered version we should ensure the sleep state is low leakage)

Hi Hugo, above you said “The ST datasheet does not make it clear whether the IO ring power is gated when the chip is in standby mode”, however here, here, and here it says that IMP pins are tri-stated during sleep. What is true?