The design guidance and reference designs for the IMP003 (especially the FCC’s) call for numerous 4.7uF and 0.1uF caps on VDD and even more of the same on VDD_PA.
Why use multiples of the same value? Would selecting a range of capacitances, say 4.7uF, 1uF, 100nF and 1nF, bypass a wider frequency range? Or are values selected and duplicates of these values required to sufficiently bypass/filter critical frequencies?
Generally, the “decades” of capacitance isn’t really required with modern SMT ceramics. The idea with the tiers was to improve the bypass frequency response at higher and higher frequencies using smaller caps - however, a well-routed SMT ceramic has low ESR across a very wide frequency range. Believe me, we did a lot of simulation of power supply networks at Apple including board & substrate extractions to simulate frequency response of bypass for DDR, and the sim team recommended nothing but big ceramics
It’s one of those rules of thumb that just won’t die…
The values on the 003 reference design (eg the FCC amy) are the ones that were used in certification testing, so they are sufficient to make it pass. If you are doing a commercial board design though, PLEASE submit it to support@ei for a review before fabbing it. We can help ensure that it works first time.
The module also has additional bypassing inside, but tends to be the lower values since they like to use 0201 and 01005 components inside the the module. That’s why you don’t need to add the 1nF outside the module.
Most of the bypassing requirements come from the silicon vendor, Broadcom, and some from the module vendor, Murata, based off of their experience, simulation and testing. When you start changing things, it’s very hard to predict, what problems, if any, you will run into.
Thanks for the advice guys.
Thanks for the offer Hugo, I contacted support not long ago who were very helpful. I have a couple things to sort at my end and I’ll be in touch.